Abstract
Image and video
signals might be corrupted by impulse noise in the process of signal
acquisition and transmission. An efficient VLSI implementation for removing
impulse noise is presented. The results show that the proposed technique
preserves the edge features and obtains excellent performances in terms of
quantitative evaluation and visual quality. The design requires only low
computational complexity and two line memory buffers. Its hardware cost is
quite low. Compared with previous VLSI implementations, our design achieves
better image quality with less hardware cost.
Block Diagram:
Objectives:
- Design of algorithm for Removal of
impulse noise for signal acquisition and transmission.
- Design and implementation of above
algorithm with different software.
- To model and build the specific 7-stage
pipeline architecture for SEPD and 5-stage pipeline architecture for RSEPD
are also developed and implemented using Verilog HDL.
- Obtain the results using Modelsim.
- Implementation of low cost VLSI over
FPGA.
Existing System
Recently, many
image denoising methods have been proposed to carry out the impulse noise
suppression some of them employ the standard median filter or its modifications
to implement denoising process.
However, these
approaches might blur the image since both noisy and noise-free pixels are
modified. The switching median filter consists of two steps: 1) impulse
detection and 2) noise filtering.
New impulse
detector (NID) for switching median filter. NID used the minimum absolute
Value of four
convolutions which are obtained by using 1-D Laplacian operators to detect
noisy pixels. A method named as differential rank impulse detector (DRID) is
presented in. The impulse detector of DRID is based on a comparison of signal
samples within a narrow rank window by both rank and absolute value. In [8],
Luo proposed a method which can efficiently remove the impulse noise (ERIN ) based on simple fuzzy impulse detection technique.
Proposed System
The real-time embedded applications, the VLSI
implementation of switching median filter for impulse noise removal is
necessary and should be considered
The cost of VLSI implementation depends mainly
on the required memory and computational complexity.Hence, less memory and few
operations are necessary for a low-cost denoising implementation. Based on
these two factors, A simple edge-preserved denoising technique (SEPD) and its
VLSI implementation for removing fixed-value impulse noise is propoesd. The
storage space needed for SEPD is two line buffers rather than a full frame
buffer. Only simple arithmetic operations, such as addition and subtraction,
are used in SEPD.
System Requirement Specifications
Hardware
requirements
- PC(Intel
Pentium Processor with more than 400 MHz)
- 256 and Above
RAM
- 80GB Hard Disk
- FPGA BOARD
Software Requirements
- Programming
language: Verilog HDL
- Model Sim
- XILINX
The Modules
- Line Buffer
- Register Bank
- Extreme Data Detector
- Edge-Oriented Noise Filter
- Impulse Arbiter
- Implementation of Reduced SPED
